1. Technical Field
The present invention relates to the manufacture of electronic circuit assemblies, and more particularly to the manufacture of circuit assemblies having electrical circuits disposed as a plurality of layers separated by dielectric material.
2. Background Art
High density circuit assemblies are typically formed as sequentially added layers of circuitry on printed circuit boards (PCBs), metal sheets, ceramic substrates and the like. Such assemblies are typically formed by full additive metalization, for example by electroless or electrolytic plating or vacuum deposition. Full metalization processes are time consuming and suffer yield problems due to the inherent thickness non-uniformity of the circuitry. Also, it is generally necessary to drill through holes and blind vias as separate intermediate operations during the manufacturing process, adding to the cost of manufacture.
One method for forming multi layer circuit boards is disclosed in U.S. Pat. No. 5,260,518 issued Nov. 9, 1993 to Tanaka et at. The manufacturing method disclosed by Tanaka et al requires that stepped holes, of increasing diameter from lower to upper conductive layers, be bored or drilled during the manufacture to provide for conductive interconnection between electrical circuits disposed on different layers of the assembly. The increasingly larger diameters of the holes are required to solve the problem of misregistration of the holes when the layers are laminated. This practice not only increases the cost and complexity of manufacturing, but because of the required larger holes; also limits the spacing, or density, of interconnection sites in the circuit assembly. Accordingly, the circuits have lower component density which requires larger board areas and increases the overall size of the circuit assembly.
Other methods of forming multiple layered electrical circuit assemblies require the use of adhesive materials to bond the electrically conductive circuit layers to dielectric separating material. For example, U.S. Pat. No. 4,420,364 issued Dec. 13, 1983 to Nukii et al describes the use of high-insulation adhesive sheets in the construction of multiple layer circuit assemblies. Likewise, U.S. Pat. No. 5,234,536 issued Aug. 10, 1993 to Parthasarathi et al requires the use of adhesive materials to bond a metal foil layer to a substrate. In both of these constructions, holes must be provided through the adhesive materials so that selected portions of spaced apart circuit layers can be interconnected. These holes must be sufficiently large so that adhesive reflow during lamination does not occlude the interconnection site. As noted above, when relatively large holes are required for circuit interconnection, the spacing and density of vias and other interconnection sites is adversely limited. Accordingly, circuit assemblies formed through the use of adhesive bonding materials generally require more space for positioning of components, resulting in relatively large board areas and increased size of electronic circuits formed thereon.
The present invention is directed to overcoming the problems set forth above. It is desirable to have a method for manufacturing multiple layered electronic circuit assemblies that does not require the drilling of stepped holes of increasing diameter to provide for conductive interconnection between electrical circuits. It is also desirable to have such a manufacturing method that does not require the use of adhesive bonding materials, so that via and interconnection holes through the insulative material can be relatively small, permitting the formation of high density circuitry on the circuit layers. It is also desirable to have a manufacturing system for the formation of multiple layered high density electronic circuit assemblies that is economical and easily automated so that previous problems with registration of respective circuits on spaced apart layers are reduced.